An expert witness and technical expert in IP litigation representing clients in (EE) Electrical Engineering cases for the telecommunications industry.

EXPERTISE:

• I/O Circuits
• Web Interface
• VLSI and Microprocessor Systems
• Communications Systems
• Wireless Systems   
• MEMS and MCM
• Mixed Signal CMOS          
• Error Correction Systems
• Analog Wireless 60GHz systems

2004 - present Tyrean LLC, Murray Hill , NJ , 07974
An Intellectual Property Consulting Company

• Registered to practice before the United States Patent and Trademark Office in Patent Cases.
• Offering Expert Witness and Technical Expert Services
• Prosecuting the patent portfolios of two startup companies containing over 50 applications.
• Determined patent strategy and formulated ideas to strengthen a patent portfolio.

Provided technical expert /expert witness consultation in the following litigation cases:

• Agere Systems v. Broadcom, Inc.
• SigmalTel Inc. v. Actions Semiconductor Co.
• Realtek Semiconductor Corp. v. Marvell Semiconductor, Inc.
• Samsung v. Ericsson
• Rembrandt Technologies v. Sharp

These consultations also included: a deposition, technological advice in support of validity infringement and patentability analysis, identification of the weaknesses in the patents presented by the opposing team, prior art search studies, and the generation of claim charts. In addition, I also provided support, analysis, and reverse engineering of several different circuits that were extracted from chip photomicrographs.

2002-2004 Agere Systems, Intellectual Property Reverse Engineering Division, Allentown , PA
Consulting Member of Technical Staff (CMTS)
Agere's patent portfolio was analyzed for claims that read on standards, systems, VLSI architectures, and analog/digital circuits. Have a thorough understanding of claim language and created numerous claim charts against competitor's products.

1980-2002 AT&T Bell System
Including Agere Systems, Bell Laboratories, Lucent Technologies and AT&T,
I was a Principle Investigator (PI) in the Wireless Systems Research Department of Bell Labs Research from 1990 to 2002. A PI is required to be self motivated and to create new ideas and concepts that can offer potential benefits for starting new businesses and endeavors.

• Developed a new low power circuit technique for decoding packets using 802.11.
• Invented the injection-locking concept applied to a CMOS LC tank circuit for data and clockrecovery of NRZ data.
• Teamed with the Technical University of Munich to design an analog MAP decoder circuit.
• Developed algorithms for noise analysis of packaged devices.
• Invented a low power current steering I/O interface that was then transferred to the AT&T Microelectronics division for a one year interim.
• Worked on an optical/electrical project that was successfully delivered to NTT.
• Invented a mixed-signal macrocell block techniques that allow circuits to compensate for process, temperature, power supply variations creating a very consistent behaving circuit method.
• Conceived and patented the CMOS LC tank circuit that is now widely used in many RF oscillators, synthesizers and PLL's.

I worked in Development for the first 10 years and delivered operating systems to clients, including:

• Leading the technical design responsible for the full custom circuit design of a telecommunication device which de-skews and frames cells for backplane transport.
• Designing and testing SRAM memory.
• Responsibility for the complete timing and signal integrity for the world's first 32 bit CMOS microprocessor.

EDUCATIONAL BACKGROUND:

• MSEE 1980, NJIT, Electrical Engineering
• BSEE 1980, NJIT, Electrical Engineering

COMMITTEE ACTIVITY:

• Intellectual Property Owners Association (IPO).     -Active Member  -Serving on the Litigation Committee
• American Intellectual Property Law Association (AIPLA).   -Active Member  -Serving on the Electronic and Computer Law Committee
• National Association of Patent Practitioners (NAPP).   -Active Member
• NJIT Industry Advisory Board Member   -Active Member
• IEEE Journal of Solid State Circuits   -Guest editor of the March 1998 issue  -Guest editor of the March 1999 issue
• IEEE Transactions on VLSI Systems  -Guest editor of the December 2000 issue
• IEEE Multi Chip Module Conference  -Served as Program Chair
• IEEE ACM International Symposium on Low Power Electronics and Design  -Served as Technical Co-Chair
• IEEE ISSCC 2000 Panel Session  -RF and High-Speed Interfaces: 50 Ohm or Freedom?
• IEEE Custom Integrated Circuits Conference  -Served as Technical Co-Chair  -Served as Program Chair

ISSUED PATENTS:

1. T.J. Gabara, Noise Controlled Output Buffer, No. 4,823,029.kldklds
2. T.J. Gabara, Integrated Circuit Power Supply Contact, No. 4,947,228.
3. T.J. Gabara, P. Metz, MOS Devices Having Improved Electrical Match, No. 5,040,035.
4. T.J. Gabara, CMOS to ECL Output Buffer, No. 5,043,605.
5. T.J. Gabara, Integrated Circuit Buffer with Improved Drive Capability, No. 5,097,148.
6. Dunlop, T.J. Gabara and S. Knauer, Digitally Controlled Element Sizing, No. 5,194,765.
7. T.J. Gabara and S. Knauer, Digitally Controlled Element Sizing, No. 5,243,229
8. Dunlop, T.J. Gabara and S. Knauer, Digitally Controlled Element Sizing, No. 5,298,800.
9. Chen, T.J. Gabara, B.L. Morris and Y. Smooha, Bipolar ESD Protection for Integrated Circuits, No. 5,304,839.
10. T.J. Gabara, Integrated Circuit Buffer With Controlled Rise/Fall Time, No. 5,311,084.
11. T.J. Gabara, Low Power Dissipating CMOS Oscillator Circuits, No. 5,396,195.
12. S. Avery, A. Dickinson, T.J. Gabara, and A. Kramer, Diode Coupled CMOS Logic Design for Quasi-Static Resistive Dissipation with Multi-Output Capability, No. 5,422,582
13. T.J. Gabara, Low-Power-Dissipation CMOS Circuits, No. 5,450,027.
14. J. Condon, R. Frye, T.J. Gabara, S. Knauer and K. Tai, Multichip Modules Having Chip-to-chip Interconnections With Reduced Signal Voltage Level and Swing, No. 5,461,333.
15. T.J. Gabara, Hybrid Data Processing System Including Pulsed-Power-Supply CMOS Circuits, No. 5,479,117.
16. T.J. Gabara, Adiabatic MOS Oscillators, No. 5,483,207.
17. Chen, T.J. Gabara, B.L. Morris and Y. Smooha, Bipolar ESD Protection For Integrated Circuits, No. 5,502,328.
18. W. C. Fischer and T. J. Gabara, Low-Power-Dissipation CMOS Circuits, No. 5,502,407.
19. T.J. Gabara, Self-Timed Oscillator Circuit Including Starting and Stopping Circuitry, No. 5,517,158
20. A.E. Dunlop, W.C. Fischer and T.J. Gabara, Closed-Loop Frequency Control of An Oscillator, No. 5,528,199.
21. T. Gabara, Hot-Clock Adiabatic Gate Using Multiple Clock Signals with Different Phases, No. 5,675,263.
22. T. Gabara, Integrated Circuit Employing Quantized Feedback, No. 5,708,389.
23. T. Gabara, Integrated Circuit Chip With Adaptive Input-Output Port, No. 5,731,711.
24. T. Gabara, Apparatus for Controlling Ground Bounce, No. 5,739,714.
25. T. Gabara and B. Morris, Communication System Having a Closed Loop Bus Structure, No. 5,757,249.
26. M. Banu, A. Dunlop, W. Fischer, T. Gabara and K. Shastri, Clock Recovery Circuit, No.5,757,872.
27. T. Gabara, Component Arrangement Having Magnetic Field Controlled Transistor, No.  5,872,384.
28. T. Gabara, Method And Component Arrangement For Enhancing Signal Integrity, No. 6,014,037.
29. T. Gabara, Low Voltage Differential Swing Interconnect Buffer Circuit, No. 5,977,796.
30. T. Gabara, Amplifier Having Improved Common Mode Voltage Range, No. 5,990,743.
31. T. Gabara, R. Rudnick, Method and Component Arrangement For Enhancing Signal Integrity, No. 6,014,037.
32. T. Gabara, High-Speed Clock-Enabled Latch Circuit, No. 6,018,260.
33. T. Gabara, Circuit arrangement for adding functionality to a circuit with reduced propagation delay, No. 6,100,743.
34. T. Gabara, M. Kothandaraman, B. Patel, Amplifier Having Improved Common Mode Voltage Range, No. 6,107,882.
35. T. Gabara, Resistor circuit with DC voltage control, No. 6,100,743.
36. T. Gabara and S. Siegel, Method and apparatus for controlling impedance, No. 6,157,215.
37. T. Gabara, Injection tuned resonant circuits, No. 6,175,285.
38. T. Gabara, Multi-input comparator, No. 6,191,623.
39. T. Gabara and A. Mujtaba, Clock Injection System, No. 6,249,192
40. T. Gabara, High Speed Clock Enabled Latch Circuit, No. 6,255,875
41. T. Gabara and King Tai, Circuit And Method For Providing Interconnections Among Individual Integrated  Circuit Chips In A Multi Chip Module, No. 6,281,590
42. T. Gabara, Apparatus and Method to Insert the Default Local Area Code into a Dialed Telephone Number, No. 6,292,557
43. T. Gabara, Asymmetrical Current Steering Output Driver With Compact Dimensions, No. 6,294,947
44. T. Gabara, Method And System Of Data Transmission Using Differential And Common Mode Data Signaling, No. 6,295,323
45. T. Gabara, Bandpass Filters With Automatic Tuning Adjustment, No. 6,307,443
46. T. Gabara, Clock Recovery Using an Injection Tuned Resonant Circuit, No. 6,317,008
47. W. Fischer and T. Gabara, Integrated Circuit Layout Design, No. 6,324,677
48. T. Gabara, Linearly-controlled Resistive Element Apparatus, No. 6,326,821
49. T. Gabara, Asymmetrical Current Steering Output Driver with Compact Dimensions, No. 6,445,241.
50. T. Gabara and A. Mujtaba, Signal Encoding for Transmission of Multiple Digital Signals Over Single Physical Medium, No. 6,456,336.
51. T. Gabara and K. Tai, Circuit and Method for Providing Interconnections among Individual Integrated Circuit Chips in a Multi-chip Module, No. 6,465,336.
52. J. Cho and T. Gabara, High Speed Latch Circuit, No. 6,472,920.
53. T. Gabara and A. Mujtaba, Multi-input Comparator, No. 6,515,533.
54. T. Gabara, Current Recycling Circuit and Method of Current Recycling, No. 6,552,581.
55. T. Gabara, Receiver for Common Mode Data Signals Carried on a Differential Interface, No. 6,575,760.
56. T. Gabara and T. Jomaa, Variable Rotational Assignment of Interconnect Levels in Integrated Circuit Fabrication, No. 6,586,281.
57. T. Gabara, Data Capture Circuit with Series Channel Sampling Structure, No. 6,597,225.
58. T. Gabara and A. Mujtaba, Signal Encoding for Transmission of Multiple Digital Signals Over Single Physical Medium,  No. 6,721,376
59. T. Gabara, Apparatus and Method for Downloading a Forwarding Telephone Number, No. 6,782,088.
60. T. Gabara and T. Jomaa, Variable Rotational Assignment of Interconnect Levels in Integrated Circuit  Fabrication, No. 6,849,937.
61. T. Gabara, Comparator circuits having non-complementary input structures, No. 6,930,516.
62. T. Gabara and S. Martin, Method for modeling noise emitted by digital circuits, No. 6,938,224.
63. A. Mujtaba and T. Gabara, Control technique for a communication system, No. 6,950,678.
64. T. Gabara, S. McLellan and D. Smith , Adjustment of a hearing aid using a phone, No. 7,024,000.
65. T. Gabara and T. Jomaa, Variable Rotational Assignment of Interconnect Levels in Integrated Circuit  Fabrication, No. 7,042,079.
66. T. Gabara, C. Huber and B. Morris, Integrated circuit with controllable test access to internal analog  signal pads of an area array, No. 7,138,814.
67. T. Gabara, Data capture circuit with self-test capability, No. 7,194,052.
68. K. Azimi and T. Gabara, Frequency selection using capacitance multiplication, No. 7,199,651.
69. T. Gabara, Mutual inductance in transformer based tank circuitry, No. 7,250,826.
70. T. Gabara and A. Lynam, Signal processing method and apparatus for ensuring a desired relationship between signals, No. 7,254,205.
71. T. Gabara and V. Prodanov, Low-power-dissipation CMOS oscillator circuits with capacitively coupled  frequency control, No. 7,274,264.
72. T. Gabara, Position-based capacity reservation in a mobile wireless system, No. 7,305,238.
73. T. Gabara, I. Lee, M. Lopez-Vallejo, and S. Mujtaba, Block processing in a maximum a posteriori processor for reduced power consumption, No. 7,353,450.
74. T. Gabara, Integrated circuit with stacked-die configuration utilizing substrate conduction, No. 7,400,047.
75. K. Chakraborty, T. Gabara, K. Stiles and B. Xu, System and method for suppressing crosstalk glitch in digital circuits, No. 7,409,659.
76. T. Gabara, Reduced eddy current loss in LC tank circuits, No. 7,429,899.
77. T. Gabara and V. Prodanov, Methods and apparatus for preventing a third party from overhearing a  telephone conversation, No. 7,471,945.
78. T. Gabara, Frequency adjustment techniques in coupled LC tank circuits, No. 7,501,903.
79. T. Gabara, Frequency adjustment techniques in coupled LC tank circuits, No. 7,508,280.
80. T. Gabara, Flux linked LC tank circuits forming distributed clock networks, No. 7,511,588.
81. T. Gabara, Assembling stacked substrates that can form cylindrical inductors and adjustable transformers, No. 7,728,427.
82. T. Gabara, Fabrication of inductors in transformer based tank circuitry, No. 7,786,836.
83. T. Gabara, Assembling stacked substrates that can form 3-D structures, No. 7,811,854.
84. T. Gabara, Levitating substrate being charged by a non-volatile device and powered by a charged capacitor or bonding wire, No. 7,812,336.
85. T. Gabara, Using multiple coulomb islands to reduce voltage stress, No. 7,863,651.
86. T. Gabara, Apparatus and method for identifying the geographic location and time in a recorded sound track by using a stealth mode technique, No. 7,894,617.
87. T. Gabara, Decelerometer formed by levitating a substrate into equilibrium, No. 7,946,174.
88. T. Gabara, Using coulomb forces to form 3-D reconfigurable antenna structures, No. 7,965,489.
89. T. Gabara, Assembling substrates that can form 3-D structures, No. 7,993,968.
90. T. Gabara, Connect and capacitor substrates in a multilayered substrate structure coupled by surface coulomb forces, No. 8,003,973.
91. T. Gabara, Using coulomb forces to study characteristics of fluids and biological samples, No. 8,008,070.
92. T. Gabara, Forming large planar structures from substrates using edge Coulomb forces, No. 8,018,009.
93. T. Gabara, Reconfigurable system that exchanges substrates using coulomb forces to optimize a parameter,  No. 8,159,809.

PUBLICATIONS:

1.  Invited Talk: “Effective Technical Writing of Patents and Invention Disclosures,” Gabara, T.J.; presented at the 2009 IEEE Custom Integrated Circuits Conference, September. 13-16, 2009, San Jose, CA.
2. “A Coulomb Force Reconfigurable System,” Gabara, T.J.; 2009 IEEE Sarnoff Symposium, March. 30-April 1, 2009, Princeton, NJ.
3.  “Intellectual Property: Startups, Claim language and the United States Patent and Trademark Office,” Gabara, T.J.; CMOS Emerging Technologies Workshop, Aug. 5-7, 2008, Vancouver BC, Canada.
4. “Noise in VLSI Technologies,” Martin, S. S.; Gabara, T.J.;Ng, Kwok; Chapter 9, The VLSI Handbook by Wai-Kai Chen, CRC Press, 2000, ISBN 0849385938.
5.  “Phantom mode signaling in VLSI systems,” Gabara, T.; Advanced Research in VLSI, 2001. ARVLSI 2001. Proceedings. 2001 Conference on,  14-16 March 2001 Page(s):88 – 100.
6.  “An analog 0.25 μm BiCMOS tailbiting MAP decoder,”  Moerz, M.; Gabara, T.; Yan, R.; Hagenauer, J.; Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International,  7-9 Feb. 2000 Page(s):356 – 357.
7. “Digitally adjustable resistors in CMOS for high-performance applications,” Gabara, T.J.; Knauer, S.C.; Solid-State Circuits, IEEE Journal of Volume 27,  Issue 8,  Aug. 1992 Page(s):1176 – 1185.
8. “Reduced ground bounce and improved latch-up suppression through substrate conduction,” Gabara, T.; Solid-State Circuits, IEEE Journal of, Volume 23,  Issue 5,  Oct. 1988 Page(s):1224 – 1232.
9.  “Electrical/Optical Issues in I/O CMOS Interfaces,” Gabara, T.J.; Optical Interconnect Workshop, Oak Ridge National Laboratory, Oak Ridge, TN, Nov. 8, 1999.
10. Trends in silicon-on-silicon multichip modules,” Frye, R.C.; Tai, K.L.; Lau, M.Y.; Gabara, T.J.; Design & Test of Computers, IEEE, Volume 10,  Issue 4,  Dec. 1993 Page(s):8 – 17.
11. The AT&T WE32200 design challenge,” Huang, V.K.L.; Seery, J.W.; Wu, W.S.; Altabet, S.K.; Killian, M.J.; Aymeloglu, S.; Gabara, T.J.; Fisher, A.L.; Hwang, I.S.; Thompson, D.W.; Micro, IEEE, Volume 9,  Issue 2,  April 1989 Page(s):14 – 25.
12. RF triode-sputtered mercury cadmium telluride thin films,” Cornely, R.H.; Suchow, L.; Gabara, T.; Diodato, P.; Electron Devices, IEEE Transactions on, Volume 27,  Issue 1,  Jan 1980 Page(s):29 – 32.
13. Metastability of CMOS master/slave flip-flops,” Gabara, T.J.; Cyr, G.J.; Stroud, C.E.; Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on, Volume 39,  Issue 10,  Oct. 1992 Page(s):734 – 740.
14. Capacitive coupling and quantized feedback applied to conventional CMOS technology,” Gabara, T.J.; Fischer, W.C.; Solid-State Circuits, IEEE Journal of, Volume 32,  Issue 3,  March 1997 Page(s):419 – 427.
15. A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection,” Sackinger, E.; Ota, Y.; Gabara, T.J.; Fischer, W.C.; Solid-State Circuits, IEEE Journal of,  Volume 34,  Issue 12,  Dec. 1999 Page(s):1944 – 1950.
16. A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection,” Sackinger, E.; Ota, Y.; Gabara, T.J.; Fischer, W.C.; Solid-State Circuits, IEEE Journal of,  Volume 35,  Issue 2,  Feb. 2000 Page(s):269 – 275.
17. A 3.25 Gb/s injection locked CMOS clock recovery cell,” Gabara, T.; Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999,  16-19 May 1999 Page(s):521 – 524.
18. Low power CMOS burst-mode laser driver for full service access network application,” Sackinger, E.; Ota, Y.; Gabara, T.J.; Fischer, W.C.; Lasers and Electro-Optics, 1999. CLEO/Pacific Rim '99. The Pacific Rim Conference on,  Volume 2,  30 Aug.-3 Sept. 1999 Page(s):519 - 520 vol.2.
19. An 0.25 μm CMOS injection locked 5.6 Gb/s clock and data recovery cell,” Gabara, T.; Integrated Circuits and Systems Design, 1999. Proceedings. XII Symposium on,  29 Sept.-2 Oct. 1999 Page(s):84 – 87.
20. 15 mW, 155 Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection,” Sackinger, E.; Ota, Y.; Gabara, T.J.; Fischer, W.C.; Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International,  15-17 Feb. 1999 Page(s):386 – 387.
21. High speed I/O buffer design for MCM,” Yang, S.J.; Chang, T.C.; Ruey-Wen Chien; Wang, E.D.; Gabara, T.J.; Tai, K.L.; Frye, R.C.; Multi-Chip Module Conference, 1997. MCMC '97., 1997 IEEE, 4-5 Feb. 1997 Page(s):52 – 57.
22. Universal guideline for CMOS I/O signal integrity,” Gabara, T.; Harrington, J.; Ran Yan; Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997,  5-8 May 1997 Page(s):353 – 356.
23. LVDS I/O buffers with a controlled reference circuit,” Gabara, T.; Fischer, W.; Werner, W.; Siegel, S.; Kothandaraman, M.; Metz, P.; Gradl, D.; ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International, 7-10 Sept. 1997 Page(s):311 – 315.
24. Lorentz force MOS transistor,” Gabara, T.; ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International,  7-10 Sept. 1997 Page(s):291 – 294.
25. A closed-form solution to the damped RLC circuit with applications to CMOS ground bounce estimation,” Gabara, T.; ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International,  23-27 Sept. 1996 Page(s):73 – 78.
26. Capacitive coupling and quantized feedback applied to conventional CMOS technology,” Gabara, T.; Fischer, W.; Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996,  5-8 May 1996 Page(s):281 – 284.
27. Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers,” Gabara, T.; Fischer, W.; Harrington, J.; Troutman, W.; Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996,  5-8 May 1996 Page(s):277 – 280.
28. Transmitters, Receivers and Detectors for High Speed Parallel Optical Interconnect Links,” Levine, B.F.; Tu, K-Y.; Gabara, T.J.; Wynn, J.D.; Duna, N.K.; Monteleone, K.; Flat Panel Display Technology/Technologies for a Global Information Infrastructure/ICs for New Age Lightwave Communications/RF Optoelectronics, 1995 Digest of the LEOS Summer Topical Meetings,  7-11 Aug. 1995 Page(s):44 – 45.
29. 18 channel 622 Mb/s CMOS receiver array for parallel optical interconnects,” Tu, K.-Y.; Gabara, T.J.; Levine, B.F.; Wynn, J.D.; Dutta, N.K.; Monteleone, K.J.; ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International,  18-22 Sept. 1995 Page(s):196 – 199.
30. An integrated system consisting of an 8×8 adiabatic-PPS multiplier powered by a tank circuit,” Gabara, T.; Fischer, W.; Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International,  15-17 Feb. 1995 Page(s):316 - 317, 387.
31. 150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection,” Dunlop, A.E.; Fischer, W.C.; Banu, M.; Gabara, T.; Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International, 15-17 Feb. 1995 Page(s):44 - 45, 338.
32. Pulsed Low Power CMOS,” T. Gabara, International Journal of High Speed Electronics and Systems, vol. 5, no. 2, pp. 159-177, June 1994.
33. Comparisons of bus transfer operations using PPS (pulsed power supply) and conventional CMOS in PWB and MCM environments,” Gabara, T.; Fischer, B.; Multi-Chip Module Conference, 1995. MCMC-95, Proceedings., 1995 IEEE,  31 Jan.-2 Feb. 1995 Page(s):118 – 122.
34. Ground Bounce Control in CMOS Integrated Circuits,” Gabara, T.; Thompson, D.; Solid-State Circuits Conference, 1988. Digest of Technical Papers. ISSCC. 1988 IEEE International, February 17-19, 1988 Page(s):88-89, 313.
35. High speed, low power CMOS transmitter-receiver system,” Gabara, T.J.; Thompson, D.W.; Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on,  3-5 Oct. 1988 Page(s):344 – 347.
36. A 200 MHz 100 K ECL output buffer for CMOS ASICs,” Gabara, T.J.; Thompson, D.W.; ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE,  17-21 Sept. 1990 Page(s):P8/5.1 - P8/5.4 .
37. A 180Mhz ASIC For High-speed Interfaces,” Thompson, D.W.; Gabara, T.J.; Stroud, C.E.; Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International,  13-15 Feb. 1991 Page(s):140 – 305.
38. Improved DC matching of CMOS circuits using Rotational Symmetry,” Gabara, T.J.; Metz, P.C.; ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International,  23-27 Sept. 1991 Page(s):P10 - 3/1-3.
39. Ground bounce and reduction techniques,” Gabara, T.J.; ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International,  23-27 Sept. 1991 Page(s):T13 - 2/1-2.
40. Metastability of CMOS master/slave flip-flops,” Gabara, T.J.; Cyr, G.J.; Stroud, C.E.; Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991,  12-15 May 1991, Page(s):29.4/1 - 29.4/6.
41. On-chip terminating resistors for high speed ECL-CMOS interfaces,” Gabara, T.J.; ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International,  21-25 Sept. 1992 Page(s):292 – 295.
42. A 600 MHz 100 K ECL output buffer fabricated in 0.9 μm CMOS,” Gabara, T.; TENCON '92. Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century. 1992 IEEE Region 10 International Conference,  11-13 Nov. 1992 Page(s):774 - 778 vol.2.
43. A 9 Gbit/s bandwidth multiplexer/demultiplexer CMOS chip,” Dunlop, A.E.; Gabara, T.J.; Fischer, W.C.; VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on,  4-6 June 1992 Page(s):68 – 69.
44. An I/O CMOS buffer set for silicon multichip module's (MCM),” Gabara, T.; Fischer, W.; Knauer, S.; Frye, R.; Tai, K.; Lau, M.; Multi-Chip Module Conference, 1993. MCMC-93, Proceedings., 1993 IEEE,  15-18 March 1993 Page(s):147 – 152.
45. Digital transistor sizing techniques applied to 100K ECL CMOS output buffers,” Gabara, T.J.; Fischer, W.; ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International, 27 Sept.-1 Oct. 1993 Page(s):456 – 459.
46. Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs,” Frye, R.C.; Gabara, T.J.; Tai, K.L.; Fischer, W.C.; Knauer, S.C.; ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International,  27 Sept.-1 Oct. 1993 Page(s):464 – 467.
47. Pulsed power supply CMOS-PPS CMOS,” Gabara, T.; Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium,  10-12 Oct. 1994 Page(s):98 – 99.
48. Quasi-static CMOS,” Gabara, T.; ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International,  19-23 Sept. 1994 Page(s):104 – 107.
49. Multi-GHz CMOS oscillators,” Gabara, T.; Fischer, B.; ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International,  19-23 Sept. 1994 Page(s):41 – 43.
50. A 27 mW CMOS RF oscillator operating at 1.2 GHz,” Gabara, T.; Tai, K.; Lau, M.; Shin Pei; Frye, R.; Sullivan, P.; Multi-Chip Module Conference, 1994. MCMC-94, Proceedings., 1994 IEEE, 15-17 March 1994 Page(s):15 – 19.

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